发明名称 Method of forming an interconnect structure having an enlarged region
摘要 A method of forming an interconnect structure that may reduce or eliminate stress induced voids is provided. In an embodiment, a via is formed below a conductive line to provide an electrical connection to an underlying conductive region. The conductive line includes a widened region above the via. The widened region serves to reduce or eliminate stress induced voids between the via and the underlying conductive region. In another embodiment, one or more redundant lines are formed extending from a conductive region, such as a contact pad, such that the redundant line does not electrically couple the conductive region to an underlying conductive region. In a preferred embodiment, the redundant lines extend from a conductive region on a side adjacent to a side having a conductive line coupled to a via.
申请公布号 US8785323(B2) 申请公布日期 2014.07.22
申请号 US201313953418 申请日期 2013.07.29
申请人 Taiwan Semiconductor Manufacturing Company, Ltd. 发明人 Wang Chien-Jung
分类号 H01L21/4763 主分类号 H01L21/4763
代理机构 Slater and Matsil, L.L.P. 代理人 Slater and Matsil, L.L.P.
主权项 1. A method of forming an interconnect structure, the method comprising: forming a via through a dielectric layer; forming a conductive line in the dielectric layer over the via, the conductive line electrically coupling a conductive region to the via; and forming a redundant line in the dielectric layer, the redundant line being in electrical contact to only the conductive region.
地址 Hsin-Chu TW