Low-power dual-edge-triggered storage cell with scan test support and clock gating circuit therefor

摘要

A storage cell having a pulse generator and a storage element is proposed. The storage element input is connected to receive a data input signal. The storage element output is connected to provide a data output signal. The storage element is operable in one of a data retention state and a data transfer state in response to a storage control signal received from the pulse generator. The pulse generator is connected to receive a clock signal with rising and falling clock signal edges and is adapted to provide control pulses in the storage control signal. Each control pulse has a leading edge and a trailing edge. The control pulses have a polarity suited to invoke the data transfer state on their leading edges. The novel feature is that the pulse generator is adapted to initiate a rising-edge control pulse when receiving a rising clock signal edge and to initiate a falling-edge control pulse when receiving a falling clock signal edge. In this way, a dual-edge-triggered flip-flop may be made using only combinatorial logic circuitry and one level- or single-edge-triggered storage element. The storage cell has low power consumption, facilitates scan testing and can be used by existing design tools and test equipment.

主权项

1. A storage cell having a data output terminal, a clock terminal, a pulse generator, a storage element and an input circuit, the storage element having a storage input and a storage output, the storage input being connected to receive a data input signal from the input circuit, the storage output being connected to provide a data output signal to the data output terminal, the storage element being operable in one of a data retention state and a data transfer state in response to a storage control signal received from the pulse generator, the pulse generator being connected to receive a clock signal with rising and falling clock signal edges from the clock terminal and being adapted to provide control pulses in the storage control signal, each control pulse having a leading edge and a trailing edge, the control pulses having a polarity suited to invoke the data transfer state on their leading edges, wherein each control pulse is one of a rising-edge control pulse and a falling-edge control pulse, and wherein the pulse generator is adapted to initiate a rising-edge control pulse when receiving a rising clock signal edge and to initiate a falling-edge control pulse when receiving a falling clock signal edge.