发明名称 Inspection device and inspection method
摘要 The present invention provides semiconductor integrated circuit, inspection device and inspection method for inspecting whether inspection target is functioning normally regardless to start-up period of a power supply voltage. The inspection device includes a reset control circuit and a tester. When a reset signal is inputted from a power-on reset circuit to a first terminal, the reset control circuit starts output of a reset execution signal having the same level as the reset signal. When a trigger signal is inputted from a control device to the second input terminal, the reset control circuit finishes the output of the reset execution signal and starts output of a release execution signal that has the same level as a reset release signal from the output terminal. The tester determines whether the power-on reset circuit is functioning normally by determining whether signals outputted from the reset control circuit are at predetermined levels.
申请公布号 US8786306(B2) 申请公布日期 2014.07.22
申请号 US201113271607 申请日期 2011.10.12
申请人 Lapis Semiconductor Co., Ltd. 发明人 Fujimoto Shuichiro
分类号 G01R31/26;G01R31/3177;G06F1/24;G11C5/14;H03K17/22 主分类号 G01R31/26
代理机构 Rabin & Berdo, P.C. 代理人 Rabin & Berdo, P.C.
主权项 1. An inspection device comprising: a trigger output section that outputs a trigger signal; a signal output section including, a first terminal, connected to an output terminal of an inspection target circuit, that outputs a first level transition signal that, using a rise of a DC voltage, transits from an initialization level, which represents a level for initializing a logic circuit when the DC voltage is applied, to an initialization release level, which represents a level for releasing an initialization state of the logic circuit,a second terminal connected to an output terminal of the trigger output section, anda third terminal connected to an input terminal of the logic circuit,wherein, the signal output section outputs, from the third terminal, a second level transition signal that transits from an initialization execution level which is the same level as the initialization level in response to the first level transition signal having the initialization level, to a release execution level which is the same level as the initialization release level in response to the trigger signal; and a determination section that determines whether the inspection target circuit is functioning normally by determining whether the signal outputted from the third terminal of the signal output section is at a predetermined level.
地址 Yokohama JP