Non-replacement gate nanomesh field effect transistor with pad regions

摘要

A gate-first processing scheme for forming a nanomesh field effect transistor is provided. An alternating stack of two different semiconductor materials is patterned to include two pad regions and nanowire regions. A semiconductor material is laterally etched selective to another semiconductor material to form a nanomesh including suspended semiconductor nanowires. A stack of a gate dielectric, a gate electrode, and a gate cap dielectric is formed over the nanomesh. A dielectric spacer is formed around the gate electrode. An isotropic etch is employed to remove dielectric materials that are formed in lateral recesses of the patterned alternating stack. A selective epitaxy process can be employed to form a source region and a drain region.

主权项

1. A semiconductor structure comprising:
a vertical stack of at least two first patterned semiconductor layers comprising a first semiconductor material and at least one second patterned semiconductor layer comprising a second semiconductor material, wherein each of said at least two first patterned semiconductor layers comprises at least one semiconductor nanowire and a pair of first pad regions adjoining said at least one semiconductor nanowire, and wherein each of said at least one second patterned semiconductor layer comprises a pair of second pad regions that are laterally spaced from each other; a gate electrode structure straddling said at least one semiconductor nanowire; a gate spacer laterally surrounding said gate electrode structure; and both a raised source region and a raised drain region comprising a semiconductor material and contacting surfaces of said at least one semiconductor nanowire and each of said first and second pad regions.