Analog memories utilizing ferroelectric capacitors

摘要

A ferroelectric memory having a plurality of ferroelectric memory cells, each ferroelectric memory cell including a ferroelectric capacitor is disclosed. The ferroelectric memory includes read and write lines and a plurality of ferroelectric memory cell select buses, one select bus corresponding to each of the ferroelectric memory cells. Each of the ferroelectric memory cells includes first and second gates for connecting the ferroelectric memory cell to the read line and the write line, respectively, in response to signals on the ferroelectric memory cell select bus corresponding to that ferroelectric memory cell. A write circuit causes a value determined by a data value having at least three states to be stored in the ferroelectric memory cell currently connected to the write line. A read circuit measures the charge stored in the ferroelectric memory cell currently connected to the read line.

主权项

1. A memory circuit comprising:
a ferroelectric capacitor that stores a charge when said ferroelectric capacitor is not powered; a reset circuit that causes said ferroelectric capacitor to store a first charge; a write circuit that receives a data value, converts that data value to a second charge that does not depend on said first charge, and causes said second charge to be added to said first charge to generate a third charge stored in said ferroelectric capacitor, said third charge being different from said first and second charges; and a read circuit that determines said third charge stored in said ferroelectric capacitor, said read circuit generating an output signal having more than two states.