System and method for guiding remedial transformations of a circuit design defined by physical implementation data to reduce needed physical corrections for detected timing violations in the circuit design

摘要

A system and method are provided for pessimism reduction of a timing database provided for optimization of a circuit design. Pessimism is reduced through generation of a hybrid graph-based static timing analysis (GBA) and path-based static timing analysis (PBA STA) database. PBA is selectively performed on the most critical GBA identified timing violations with the goal of reducing erroneous pessimism in operational timing characteristics passed on to the physical implementation corrective optimizer module to thereby reduce unnecessary fixing and transformations upon the circuit design to correspondingly reduce design time, temporary storage space, needed processing power for timing closure and to result in a finished operable and tangible circuit device with reduced area, power requirements, and decreased cost.

主权项

1. A method for guiding remedial transformations of a circuit design defined by physical implementation data to reduce needed physical corrections for detected violations in the circuit design, the method comprising:
establishing at least one processor coupled to a memory, the memory including physical implementation data for a circuit design including a plurality of timing paths, each path having at least one node thereon; executing a graph-based timing analysis in the at least one processor to receive and analyze the physical implementation data in operational timing, said graph-based timing analysis generating a graph-based data store identifying a candidate set of defective nodes of the circuit design responsive to detection of an operational timing defect in said circuit design, said graph-based timing analysis generating operational timing characteristic data including an identification and magnitude of the operational timing defect for each of said candidate set of defective nodes; executing a path-based timing analysis on said candidate set of defective nodes to generate a path-based data store identifying operational timing characteristics of said candidate set of defective nodes; and, selectively replacing operational timing characteristics of said graph-based data store with operational timing characteristics of said candidate set of defective nodes from said path-based data store to generate a hybrid graph-based and path-based data store of said circuit design.