Testing system for integrated circuits including components for receiving clock signals corresponding to different clock domains

摘要

A system for testing an integrated circuit including components for receiving clock signals corresponding to different clock domains includes a pin of the integrated circuit to receive a test clock signal for components included in different clock domains, clock gating cells integrated in the integrated circuit to direct said test clock signal from the pin towards components included in respective clock domains and, coupled to each of the gating cells, a dedicated flip-flop for a respective clock domain, the dedicated flip-flop being also integrated in the integrated circuit to effect on the cell to which it is coupled a clock gating function during testing of the integrated circuit.

主权项

1. A system for testing an integrated circuit including components for receiving clock signals corresponding to different clock domains, the system including:
a pin of the integrated circuit to receive a test clock signal for components included in different clock domains; clock gating cells integrated in the integrated circuit to direct said test clock signal from said pin towards components included in respective clock domains; coupled to each of said gating cells, a dedicated flip-flop for a respective clock domain, said dedicated flip-flop being also integrated in the integrated circuit to effect on the cell to which it is coupled a clock gating function during test of the integrated circuit; and a logic gate interposed between said dedicated flip-flop and said clock gating cell coupled thereto to effect a gating function based on a scan enable signal by correspondingly managing generation of test patterns for the circuit, wherein the output of said logic gate is feedback connected to the D input of said dedicated flip-flop.