| 摘要 |
Yield loss resulting from peripheral circuit failure while screening memory arrays for aging effects by performing memory read and write margin testing at a minimum operating voltage is prevented by operating the peripheral circuitry at nominal operating voltages during the screening for aging effects. An integrated circuit including one or more memory bit cells, includes circuitry to change the voltage applied to the supply rails of bit cells and the voltage applied to the word-line drivers relative to each other in order to facilitate improved screening for read and write margins. In normal operation the supply rails for word-line drivers and bit cells are nominally the same. In a write margin test mode the voltage on the supply rail of word-line drivers is lower than the voltage on the supply rail of the bit cells. In a read margin test mode the voltage on the supply rail of word-line drivers is higher than the voltage on the supply rail of the bit cells. By targeting the read and write margins separately, test coverage of both the aging effects and operating conditions can be achieved by tuning different voltage deltas between the wordline and the array power. |
