发明名称 REDUCING OUTPUT VOLTAGE RIPPLE OF POWER SUPPLIES
摘要 Reducing output voltage ripple of power supplies. In some embodiments, an electronic circuit may include a first node configured to receive an input signal proportional to an output voltage produced by a power supply, a second node configured to receive a reference voltage configured to alternate between two voltage values during operation of the power supply, and a third node configured to output an enabling signal configured to control the operation of the power supply in response to a comparison between the input signal and the reference voltage. In other embodiments, a method may include turning on a power supply in response to a falling ripple being smaller than a first reference voltage value, and turning off the power supply in response to a rising ripple being greater than a second reference voltage value, where the second reference voltage value is smaller than the first reference voltage value.
申请公布号 US2014197807(A1) 申请公布日期 2014.07.17
申请号 US201313742540 申请日期 2013.01.16
申请人 Terçariol Walter L.;Saez Richard Titov Lara;Salvarani Alfredo;Kickhofel Remerson Stein 发明人 Terçariol Walter L.;Saez Richard Titov Lara;Salvarani Alfredo;Kickhofel Remerson Stein
分类号 G05F1/46 主分类号 G05F1/46
代理机构 代理人
主权项 1. An electronic circuit, comprising: a first node configured to receive an input signal proportional to an output voltage produced by a power supply; a second node configured to receive a reference voltage, the reference voltage configured to alternate between two voltage values during operation of the power supply; and a third node configured to output an enabling signal configured to control the operation of the power supply in response to a comparison between the input signal and the reference voltage.
地址 Campinas BR