Enforcement of Semiconductor Structure Regularity for Localized Transistors and Interconnect

摘要

A global placement grating (GPG) is defined for a chip level to include a set of parallel and evenly spaced virtual lines. At least one virtual line of the GPG is positioned to intersect each contact that interfaces with the chip level. A number of subgratings are defined. Each subgrating is a set of equally spaced virtual lines of the GPG that supports a common layout shape run length thereon. The layout for the chip level is partitioned into subgrating regions. Each subgrating region has any one of the defined subgratings allocated thereto. Layout shapes placed within a given subgrating region in the chip level are placed in accordance with the subgrating allocated to the given subgrating region. Non-standard layout shape spacings at subgrating region boundaries can be mitigated by layout shape stretching, layout shape insertion, and/or subresolution shape insertion, or can be allowed to exist in the final layout.

主权项

1. A semiconductor device, comprising:
a first linear-shaped conductive structure defined in a given chip level of the semiconductor device, the first linear-shaped conductive structure having a lengthwise centerline oriented in a first direction, the first linear-shaped conductive structure having a width measured in a second direction perpendicular to the first direction; a second linear-shaped conductive structure defined in the given chip level of the semiconductor device, the second linear-shaped conductive structure having a lengthwise centerline oriented in the first direction, the second linear-shaped conductive structure having a width measured in the second direction; and a third linear-shaped conductive structure defined in the given chip level of the semiconductor device, the third linear-shaped conductive structure having a lengthwise centerline oriented in the first direction, the third linear-shaped conductive structure having a width measured in the second direction, the width of the first linear-shaped conductive structure substantially equal to the width of the third linear-shaped conductive structure, the width of the second linear-shaped conductive structure greater than the width of the first linear-shaped conductive structure, at least a portion of the second linear-shaped conductive structure positioned in a side-by-side manner with at least a portion of the first linear-shaped conductive structure, the side-by-side positioned portions of the first and second linear-shaped conductive structure separated from each other by a first distance as measured in the second direction, and at least a portion of the second linear-shaped conductive structure positioned in a side-by-side manner with at least a portion of the third linear-shaped conductive structure, the side-by-side positioned portions of the second and third linear-shaped conductive structures separated from each other by the first distance as measured in the second direction.