| 发明名称 |
SELECTING MEMORY CELLS |
| 摘要 |
A memory device comprises memory cells arranged in rows and columns, and source lines associated with memory sections, each of which includes a plurality of memory cells. Source terminals of transistors included in the memory cells in a first memory section are physically coupled to a first source line that is distinct from other source lines associated with other memory sections on a same row of the memory device as the first memory section. Gate terminals of transistors included in memory cells in a row share a common wordline configured for providing a signal to the gate terminals. |
| 申请公布号 |
US2014198571(A1) |
申请公布日期 |
2014.07.17 |
| 申请号 |
US201313921567 |
申请日期 |
2013.06.19 |
| 申请人 |
Atmel Corporation |
发明人 |
Wu Tsung-Ching;Chern Geeng-Chuan;Schumann Steven;Ng Philip S. |
| 分类号 |
G11C16/06 |
主分类号 |
G11C16/06 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A memory device comprising:
memory cells arranged in rows and columns; and source lines associated with memory sections, wherein a memory section includes a plurality of memory cells, wherein source terminals of transistors included in the memory cells in a first memory section are physically coupled to a first source line that is distinct from other source lines associated with other memory sections on a same row of the memory device as the first memory section, and wherein gate terminals of transistors included in memory cells in a row share a common wordline configured for providing a signal to the gate terminals. |
| 地址 |
San Jose CA US |
