发明名称 BUMP STRUCTURAL DESIGNS TO MINIMIZE PACKAGE DEFECTS
摘要 A method of forming a chip package includes providing a chip with a plurality of first copper post bumps having a first height of copper post. The method also includes providing a substrate with a plurality of second copper post bumps having a second height of copper post. The method further includes bonding the plurality of first copper post bumps to the plurality of second copper post bumps by reflowing solder layers on the plurality of first copper post bumps and the plurality of second copper post bumps together to form a first copper post bump structure of the chip package. The first copper post bump structure has a standoff, wherein a ratio of a sum of the first height of copper post and the second height of copper post to the standoff is equal to or greater than about 0.6 and less than 1.
申请公布号 US2014199812(A1) 申请公布日期 2014.07.17
申请号 US201414210817 申请日期 2014.03.14
申请人 TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. 发明人 LIN Jing-Cheng;HUANG Cheng-Lin
分类号 H01L21/56 主分类号 H01L21/56
代理机构 代理人
主权项 1. A method of forming a chip package, comprising: providing a chip with a plurality of first copper post bumps, wherein the plurality of first copper post bumps have a first height of copper post; providing a substrate with a plurality of second copper post bumps, wherein the plurality of second copper post bumps have a second height of copper post; bonding the plurality of first copper post bumps to the plurality of second copper post bumps by reflowing solder layers on the plurality of first copper post bumps and the plurality of second copper post bumps together to form a first copper post bump structure of the chip package, wherein the first copper post bump structure has a standoff, wherein a ratio of a sum of the first height of copper post and the second height of copper post to the standoff is equal to or greater than about 0.6 and less than 1.
地址 Hsinchu TW