A high speed dram architecture with uniform access latency

摘要

A Dynamic Random Access Memory (DRAM) performs, read, write, and refresh operations. The DRAM includes a plurality of sub-arrays (504), each having a plurality of memory cells (604), each of which is coupled with a complementary bit line pair and a word line. The DRAM further includes a word line enable device (911) for asserting a selected one of the word lines and a column select device for asserting a selected one of the bit line pairs. A timing circuit (908,910,912) is provided for controlling the word line enable device, the column select device, and the read, write, and refresh operations in response to a word line timing pulse (WTPi). The read, write, and refresh operation are performed in the same amount of time.