Efficient method to analyze RTL structures that cause physical implementation issues based on rule checking and overlap analysis

摘要

This invention provides a method for detecting physical implementation hot-spots in a pre-placement integrated circuit design. The method first identifies physical issues at an object level. Physical issues include timing, routing congestion, clocking, scan, power, and thermal. The method then analyzes these physical issues over a collection of connected logic cell and large cell instances and determines a physical implementation hot-spot severity based on the number and severity of physical issues as well as the number of objects in the related collection.

主权项

1. A method implemented in a computing system for analyzing physical implementation issues in a pre-placement integrated circuit design, comprising:
receiving in the system a hardware description of a pre-placement integrated circuit design; analyzing for each logic cell in the received hardware description a set of physical issue metrics and identifying any logic cell having a value for at least one such metric exceeding a corresponding specified threshold; measuring for each identified logic cell a physical issue severity based on the values of all metrics exceeding said corresponding thresholds, the physical issue severity for any identified logic cell being computed as a sum of normalized metric values for that logic cell; determining any collection of identified logic cells based on proximity of the respective identified logic cells with related physical issue metrics; analyzing for each determined collection a hotspot severity metric based on the physical issue severity of each logic cell in the collection; and outputting a physical implementation hotspot severity report for the analyzed collections.