发明名称 |
Last branch record indicators for transactional memory |
摘要 |
In one embodiment, a processor includes an execution unit and at least one last branch record (LBR) register to store address information of a branch taken during program execution. This register may further store a transaction indicator to indicate whether the branch was taken during a transactional memory (TM) transaction. This register may further store an abort indicator to indicate whether the branch was caused by a transaction abort. Other embodiments are described and claimed. |
申请公布号 |
US8782382(B2) |
申请公布日期 |
2014.07.15 |
申请号 |
US201313786724 |
申请日期 |
2013.03.06 |
申请人 |
Intel Corporation |
发明人 |
Rajwar Ravi;Lachner Peter;Knauth Laura A.;Lai Konrad K. |
分类号 |
G06F9/38 |
主分类号 |
G06F9/38 |
代理机构 |
Trop, Pruner & Hu, P.C. |
代理人 |
Trop, Pruner & Hu, P.C. |
主权项 |
1. A processor comprising:
a decoder to receive and decode instructions; at least one execution unit to execute decoded instructions; and at least one last branch record (LBR) register to store at least one of source and destination address information of a branch taken during program execution, the at least one LBR register further including a transaction indicator to indicate whether the branch was taken during a transactional memory (TM) transaction. |
地址 |
Santa Clara CA US |