Spurious induced charge cleanup for one time programmable (OTP) memory

摘要

A high density, low voltage, and low-power one time programmable (OTP) memory is based on core cells with a one transistor design. A CLEAN pulse is directed to a single shunt device at the output of the column decoder so spurious charges that may have been stored in the floating nodes can be cleaned up. Such arrangement also allows for the simultaneous initialization of bit lines, data lines, and sensing lines to zero. Core area layout size is substantially reduced, and operational power requirements are exceeding low making these particularly suitable in HF and UHF RFID applications.

主权项

1. A method for sensing and reading core cells in memories (300), comprising:
configuring each core cell in a memory array block to include a single transistor N with only a first end of a floating node capacitor C connected to its drain, wherein rows of transistors N and capacitors C are interconnected by their gates to a write select (WS) line, and a second end of capacitor C is connected to a write program (WP) line, and the sources of each of transistors N in columns are interconnected by a corresponding bit line (BL) to a switch in a column decoder; shunting a common line between all the column switches in the column decoder and the BL-input of a voltage comparator in a sense amplifier with a CLEAN pulse transistor NM; and simultaneously cleaning any stored charges in the floating nodes and initializing the bit lines, data lines, and sensing lines to zero by pulsing a CLEAN pulse transistor NM on while its WS and WP lines are held low; wherein, DC currents are prevented from flowing in bit line BLs when reading a core cell and such thereby conserves overall power consumption.