Dynamic and idle power reduction sequence using recombinant clock and power gating

摘要

Methods and apparatus for dynamic and/or idle power reduction sequence using recombinant clock and/or power gating are described. In one embodiment, at least a portion of an Integrated Input/Output (IIO) logic is to enter a lower power consumption state based on a power reduction sequence. Other embodiments are also disclosed.

主权项

1. A integrated circuit device comprising:
a processor; and Integrated Input/Output (IIO) logic coupled to the processor, wherein at least a portion of the IIO logic is to enter a lower power consumption state based on a power reduction sequence, wherein the processor and the IIO logic are to each comprise sideband control logic to provide sideband communication support in lieu of removal of a physical link layer circuitry.