Shift register

摘要

A shift register is formed by connecting unit circuits 11 in multi-stage. One electrode of a capacitor Cap2 in the unit circuit 11 is connected to the gate terminal (node N1) of a transistor T2, and the other connected to a node N2. A compensation circuit composed of transistors T3 to T5 provides a clock signal CKB to the node N2 when the node N1 potential is at low level, and applies a low-level potential to the node N2 when the node N1 potential is at high level. Accordingly, even when the gate potential of the transistor T2 changes with a change in a clock signal CK, a signal that cancels out the change is provided through the capacitor Cap2, stabilizing the gate potential of the transistor T2. Thus, a change in the control terminal potential of an output transistor associated with a change in a clock signal is prevented.

主权项

1. A shift register that has a configuration in which a plurality of unit circuits are connected in multi-stage, and that operates based on a plurality of clock signals, wherein
each of the unit circuits includes:
an output transistor including a control terminal, a first conduction terminal to which a clock signal is provided, and a second conduction terminal connected to an output node;a set transistor that applies an on-potential to the control terminal of the output transistor, according to a set signal provided thereto;a reset transistor that applies an off-potential to the control terminal of the output transistor, according to a reset signal provided thereto;a capacitor including one electrode connected to the control terminal of the output transistor and including another electrode connected to a first node; anda compensation circuit that provides an opposite-phase clock signal of opposite phase to the clock signal provided to the output transistor, to the first node when a control terminal potential of the output transistor is an off-potential, and applies an off-potential to the first node when the control terminal potential is an on-potential, in order to prevent a change in the control terminal potential of the output transistor associated with a change in the clock signal.