发明名称 Semiconductor chip
摘要 In a case where a semiconductor chip is mounted over a first package, 80 pads are coupled to 80 terminals of the package, and in a case where the semiconductor chip is mounted over a second package, 100 pads are coupled to 100 terminals of the second package. An internal circuit of the semiconductor chip operates as a microcomputer with 80 terminals in a case where electrodes are insulated from each other and operates as a microcomputer with 100 terminals in a case where the electrodes are shorted therebetween by an end part of a bonding wire. Therefore, a dedicated pad for setting the number of terminals of the packages is no longer required.
申请公布号 US8779795(B2) 申请公布日期 2014.07.15
申请号 US201213556550 申请日期 2012.07.24
申请人 Renesas Elecronics Corporation 发明人 Takahashi Yuta
分类号 G01R31/02 主分类号 G01R31/02
代理机构 Foley & Lardner LLP 代理人 Foley & Lardner LLP
主权项 1. A semiconductor chip mountable over a desired one of a first package having N-number (N is a natural number) of first terminals and a second package having M-number (M is an integer larger than N) of second terminals, the semiconductor chip comprising N-number of first pads and (M−N)-number of second pads, wherein, in a case where the semiconductor chip is mounted over the first package, the N-number of first pads are respectively coupled to the N-number of first terminals via N-number of bonding wires, and in a case where the semiconductor chip is mounted over the second package, the N-number of first pads and the (M−N)-number of second pads are respectively coupled to the M-number of second terminals via M-number of bonding wires, wherein a selected second pad of the (M−N)-number of second pads is divided into first and second electrodes insulated from each other, and wherein the first and second electrodes are arranged at a predetermined interval therebetween, and when a corresponding second pad is coupled to the corresponding second terminal via the bonding wire, short by an end part of the bonding wire occurs, the semiconductor chip further comprising an internal circuit operating as a first semiconductor device having the N-number of first terminals in a case where the first and second electrodes are insulated from each other and operating as a second semiconductor device having the M-number of second terminals in a case where the first and second electrodes are shorted therebetween.
地址 Kanagawa JP