Wafer level package and methods of fabricating the same

摘要

In one embodiment, a wafer level package includes a rerouting pattern formed on a semiconductor substrate and a first encapsulant pattern overlying the rerouting pattern. The first encapsulant pattern has a via hole to expose a portion of the rerouting pattern. The package additionally includes an external connection terminal formed on the exposed portion of the rerouting pattern. An upper section of the sidewall and a sidewall of the external connection terminal may be separated by a gap distance. The gap distance may increase toward an upper surface of the encapsulant pattern.

主权项

1. A wafer level package comprising:
a rerouting pattern formed on a semiconductor substrate; a first encapsulant pattern overlying the rerouting pattern, the first encapsulant pattern having a via hole to expose a portion of the rerouting pattern; and an external connection terminal formed on the exposed portion of the rerouting pattern, wherein the via hole has a sidewall, an upper section of the sidewall and a sidewall of the external connection terminal separated by a gap distance, the gap distance increasing toward an upper surface of the encapsulant pattern; and wherein the wafer level package further comprises: a chip pad and a fuse box which are formed on the semiconductor substrate; and a passivation layer pattern, a first polymer layer pattern, and a second polymer layer pattern which are sequentially formed between the semiconductor substrate and the rerouting pattern, wherein the chip pad is exposed through the passivation layer pattern, the first polymer layer pattern, and the second polymer layer pattern and contacts the rerouting pattern, and the fuse box is exposed through the passivation layer pattern and the first polymer layer pattern and directly contacts the second polymer layer pattern.