Stress-aware design for integrated circuits comprising a stress inducing structure and keep out zone

摘要

A method of circuit design involving an integrated circuit (IC) having an interposer can include identifying an active resource implemented within the IC within a region of the interposer exposed to an amount of stress that exceeds a normalized amount of stress on the interposer and selectively assigning an element of the circuit design to be implemented within the IC to the active resource according to a stress-aware analysis of the circuit design as implemented within the IC.

主权项

1. An integrated circuit (IC) comprising:
a first die comprising a stress inducing structure, wherein the first die comprises:
a first zone characterized by a substantially normalized stress throughout the first zone, anda second zone induced by the stress inducing structure and characterized by a higher than normalized stress throughout the second zone; and a second die mounted on a surface of the first die, wherein the stress inducing structure comprises a die attachment perimeter defined by an outer edge of the second die on the first die, and wherein the first die comprises a keep out zone defined by an internal perimeter within the die attachment perimeter and an external perimeter external to the die attachment perimeter.