发明名称 PRBS test memory interface considering DDR burst operation
摘要 A method of testing an interconnect between an electronic component and an external memory comprises receiving a data word having data bits and translating the data word into multiple cycles. The multiple cycles are transmitted through the interconnect to the external memory one after another such that a value of the data bit being transmitted is switched for each cycle. In another embodiment, an electronic component comprises an interface, a translation unit, and a test module. The translation module is configured to receive a burst from the external memory through the interface and is configured to translate the burst into a data word. The test module is configured to receive the data word from the translation module and is configured to compare the data word to a test pattern to detect an interconnect defect.
申请公布号 US8782475(B2) 申请公布日期 2014.07.15
申请号 US201213730284 申请日期 2012.12.28
申请人 Futurewei Technologies, Inc. 发明人 Wang Zhiyuan;Wang Pu;Wu Qi;Sun Yufang;Wang Lisheng;Li Qixin
分类号 G01R31/28;G01R31/3183 主分类号 G01R31/28
代理机构 Conley Rose, P.C. 代理人 Conley Rose, P.C. ;Rodolph Grant;Beaulieu Nicholas K.
主权项 1. A method of testing an interconnect between an electronic component and an external memory comprising: receiving a data word having data bits; translating the data word into multiple cycles, wherein each cycle identifies one of the data bits that is to be transmitted across the interconnect in the cycle; and transmitting the multiple cycles through the interconnect to the external memory one after another, wherein a value of the data bit being transmitted is switched for each cycle.
地址 Plano TX US