Scan test of die logic in 3D ICs using TSV probing

摘要

A test architecture for 3D ICs is provided in which Through-Silicon-Vias and die logic can be tested pre-bonding dies in the stack for the 3D ICs. Post-bond scan test architecture is reconfigured to be accessed during pre-bond testing through using stratigically placed MUXs and TSVs. By connecting post-bond architecture including scan flops and boundary registers to gated scan flops used in TSV testing, an internal chain of scan flops such as typically used in post-bond testing can be selectively connected to gated scan flops connected to one end of each TSV for pre-bond testing of the internal logic through the TSVs.

主权项

1. An on-chip test architecture comprising:
a scan chain for connecting to internal logic; a receiving boundary scan flop for receiving post-bond scan input; a sending boundary scan flop for receiving and outputting post-bond scan output; a plurality of gated scan flops, each gated scan flop of the plurality of gated scan flops being connected to a corresponding through silicon via (TSV), wherein the plurality of gated scan flops comprises:
a sending gated scan flop for receiving pre-bond scan output and outputting the pre-bond scan output through its connected TSV, anda receiving gated scan flop for receiving a pre-bond scan input through its connected TSV; a first multiplexer (MUX) selectively connecting the receiving gated scan flop to an input of the scan chain; and a second MUX selectively connecting an output of the scan chain to the sending gated scan flop.