Semiconductor device

摘要

A second conduction-type MIS transistor in which a source is coupled to a second power source over the surface of a first conduction-type well and a drain is coupled to the open-drain signal terminal is provided. A second conduction-type first region is provided at both sides of the MIS transistor in parallel with a direction where the electric current of the MIS transistor flows and coupled to the open-drain signal terminal. The whole these components are surrounded by a first conduction-type guard ring coupled to the second power source and the outside surrounded by the first conduction-type guard ring is further surrounded by a second conduction-type guard ring coupled to a first power source. Thereby, the semiconductor device is capable of achieving ESD protection of an open-drain signal terminal having a small area and not providing a protection element between power source terminals.

主权项

1. A semiconductor device comprising:
a first and a second power source terminals; an open-drain signal terminal; a first conduction-type well provided over a surface of a semiconductor substrate; at least one second conduction-type MIS (Metal-insulator-Semiconductor) transistors in which a source region provided over a surface of the first conduction-type well is coupled to the second power source terminal and in which a drain region provided over the surface of the first conduction-type welt is coupled to the open-drain signal terminal; a pair of second conduction-type first regions provided in parallel with a first direction where electric current of the at least one second conduction-type MIS transistors flows over the surface of the first conduction-type well, and located at both sides of the at least one second conduction-type MIS transistors along a second direction which intersects at right angles to the first direction and each of the second conduction-type first regions is coupled to the open-drain signal terminal; a first conduction-type guard ring provided over the surface of the first conduction-type well and in an outer circumferential part of the first conduction-type well surrounding the at least one second conduction-type MIS transistors and the pair of second conduction-type first regions and coupled to the second power source terminal, wherein the first conduction-type guard ring has higher concentration than that of the first conduction-type well; a second first conduction-type guard ring provided over the surface of the semiconductor substrate further surrounding the first conduction-type guard ring from the outside and coupled to the first power source terminal; and a protection element between the first power source terminal and the second power source terminal.