发明名称 |
TFT substrate and method for producing TFT substrate |
摘要 |
An object of the invention is to provide a TFT substrate and a method for producing a TFT substrate which is capable of drastically reducing the production cost by decreasing the number of steps in the production process and improving production yield. A TFT substrate comprises: a substrate; a first oxide layer formed above the substrate; a second oxide layer formed above the first oxide layer with a channel part interposed therebetween; gate insulating film formed above the substrate, the first oxide layer and the second oxide layer; a gate electrode and a gate wire formed above the gate insulating film. |
申请公布号 |
US8778722(B2) |
申请公布日期 |
2014.07.15 |
申请号 |
US201113216583 |
申请日期 |
2011.08.24 |
申请人 |
Idemitsu Kosan Co., Ltd. |
发明人 |
Inoue Kazuyoshi;Yano Koki;Tanaka Nobuo |
分类号 |
H01L29/72 |
主分类号 |
H01L29/72 |
代理机构 |
Millen, White, Zelano & Branigan, P.C. |
代理人 |
Millen, White, Zelano & Branigan, P.C. |
主权项 |
1. A method for producing a TFT substrate comprising the steps of:
stacking a first oxide layer, a second oxide layer and a first resist in this order on a substrate, and forming the first resist in a predetermined shape by half-tone exposure; patterning the second oxide layer and the first oxide layer by an etching method using the first resist to form a source wire, a drain wire, a source electrode, a drain electrode and a pixel electrode; after reforming the first resist, selectively patterning the second oxide layer by an etching method using the first resist to form a channel part; stacking a gate insulating film, a gate electrode/wire layer and a second resist in this order on the substrate, the first oxide layer and the second oxide layer, and forming the second resist in a predetermined shape by half-tone exposure; patterning the gate electrode/wire layer and the gate insulating film by an etching method using the second resist to expose a source/drain wire pad and the pixel electrode; and after reforming the second resist, selectively patterning the gate electrode/wire layer by an etching method using the second resist to form a gate electrode and a gate wire. |
地址 |
Tokyo JP |