DRAM with dual level word lines

摘要

A top semiconductor layer and conductive cap structures over deep trench capacitors are simultaneously patterned by an etch. Each patterned portion of the conductive cap structures constitutes a conductive cap structure, which laterally contacts a semiconductor material portion that is one of patterned remaining portions of the top semiconductor layer. Gate electrodes are formed as discrete structures that are not interconnected. After formation and planarization of a contact-level dielectric layer, passing gate lines are formed above the contact-level dielectric layer in a line level to provide electrical connections to the gate electrodes. Gate electrodes and passing gate lines that are electrically connected among one another constitute a gate line that is present across two levels.

主权项

1. A semiconductor structure comprising:
a trench capacitor embedded in a substrate and comprising an inner electrode, a node dielectric, and an outer electrode; a conductive strap structure in contact with, and overlying, said inner electrode; an access transistor that comprises
a source region and a drain region that are located in a semiconductor material portion in said substrate, wherein said source region is in contact with said conductive strap structure, anda gate electrode overlying a body region of said semiconductor material portion; a passing gate line overlying a portion of said conductive strap structure and contacting another gate electrode of another access transistor; and a contact-level dielectric layer embedding said gate electrode and said another gate electrode, wherein said passing gate line is located above said contact-level dielectric layer.