发明名称 |
Semiconductor memory device including initialization signal generation circuit |
摘要 |
An initialization signal generation circuit includes: an initialization signal output unit configured to generate an initialization signal which is enabled during at least a portion of an auto refresh operation period of the initialization mode, in response to a flag signal; a refresh signal generation unit configured to generate a preliminary refresh signal and a refresh counting signal having the same period as the auto refresh signal in response to the flag signal and an auto refresh signal; and a counter unit configured to count a counting signal in response to the refresh counting signal and generate a counting initialization signal, which is delayed by at least a pulse width of the refresh counting signal, after a time point where a combination of the counting signal becomes a preset combination. |
申请公布号 |
US8780662(B2) |
申请公布日期 |
2014.07.15 |
申请号 |
US201113341524 |
申请日期 |
2011.12.30 |
申请人 |
SK Hynix Inc. |
发明人 |
Lee Eun Ryeong |
分类号 |
G11C7/00;G11C11/406;G11C7/22;G11C7/10 |
主分类号 |
G11C7/00 |
代理机构 |
William Park & Associates Patent Ltd |
代理人 |
William Park & Associates Patent Ltd |
主权项 |
1. An initialization signal generation circuit comprising:
an initialization signal output unit configured to generate an initialization signal which is enabled during at least a portion of an auto refresh operation period of an initialization mode, in response to a flag signal; a refresh signal generation unit configured to generate a preliminary refresh signal and a refresh counting signal having the same period as an auto refresh signal in response to the flag signal and the auto refresh signal; and a counter unit configured to count a counting signal in response to the refresh counting signal and generate a counting initialization signal, which is delayed by at least a pulse width of the refresh counting signal, after a time point where a combination of the counting signal becomes a preset combination. |
地址 |
Gyeonggi-do KR |