Hybrid PLL/FLL circuit to provide a clock

摘要

Clock circuits are presented for providing a clock signal using multiple reference clock signals, including a PLL operating from a PLL reference clock signal, an FLL operating from an FLL reference clock signal, and a multiplexer circuit that selectively provides up and down signals from either a PFD of the PLL or the FLL to a charge pump of the PLL according to a reference clock select signal.

主权项

1. A circuit for selectively providing a clock signal according to one of a plurality of reference clock signals, comprising:
a locking circuit, comprising:
a phase frequency detector (PFD), comprising:
a first PFD input to receive a locking circuit reference clock signal,a second PFD input to receive a feedback clock signal,a first PFD output providing a locking circuit up signal, anda second PFD output providing a locking circuit down signal,a control circuit with a first control circuit input to receive an up signal, a second control circuit input to receive a down signal, and a control circuit output providing a control output signal,a controlled oscillator providing an oscillator output clock signal having a frequency determined at least partially according to the control output signal from the control circuit, anda feedback circuit providing the feedback clock signal to the PFD at least partially according to the oscillator output clock signal from the controlled oscillator; a frequency lock loop (FLL), comprising:
a first FLL input to receive an FLL reference clock signal,a second FLL input to receive an FLL feedback clock signal,a first FLL output providing an FLL up signal, anda second FLL output providing an FLL down signal; and a multiplexer circuit configured to selectively provide one of the locking circuit up signal and the FLL up signal to the first control circuit input according to a reference clock select signal, and to selectively provide one of the locking circuit down signal and the FLL down signal to the second control circuit input according to the reference clock select signal, wherein the multiplexer circuit comprises: a first multiplexer, comprising:
a first input coupled to receive the FLL up signal from the first FLL output,a second input coupled to receive the locking circuit up signal from the first PFD output, anda first multiplexer output configured to selectively provide one of the locking circuit up signal and the FLL up signal to the first control circuit input according to the reference clock select signal; and a second multiplexer, comprising:
a first input coupled to receive the FLL down signal from the second FLL output,a second input coupled to receive the locking circuit down signal from the second PFD output, anda second multiplexer output configured to selectively provide one of the locking circuit down signal and the FLL down signal to the second control circuit input according to the reference clock select signal.