| 发明名称 | Memory and test method for memory | ||
| 摘要 | A test method for a memory having first and second cell arrays, first compressed data obtained by compressing output data of the first cell array and output data of the second cell array is outputted. When the first compressed data represents that a fail exists, output data of one of the first and second cell arrays is locked as normal data, and second compressed data obtained by compressing the normal data and output data of the other of the first and second cell arrays is outputted. | ||
| 申请公布号 | US8782476(B2) | 申请公布日期 | 2014.07.15 |
| 申请号 | US201113338591 | 申请日期 | 2011.12.28 |
| 申请人 | Hynix Semiconductor Inc. | 发明人 | Kim Dae-Suk |
| 分类号 | G11C29/00;G11C29/56;G11C29/48;G11C29/44;G11C29/50 | 主分类号 | G11C29/00 |
| 代理机构 | IP & T Group LLP | 代理人 | IP & T Group LLP |
| 主权项 | 1. A test method for a memory having first and second cell arrays, comprising: outputting first compressed data obtained by compressing output data of the first cell array and output data of the second cell array; and locking one of the output data of the first cell array and the output data of the second cell array as normal data and outputting second compressed data obtained by compressing the normal data and the other of the output data of the first cell array and the output data of the second cell array, when the first compressed data represents that a fail exists. | ||
| 地址 | Gyeonggi-do KR | ||