Methods for fabricating integrated circuits having low resistance metal gate structures

摘要

Methods for fabricating integrated circuits having low resistance metal gate structures are provided. One method includes forming a metal gate stack in a FET trench formed in a FET region. The metal gate stack is etched to form a recessed metal gate stack and a recess. The recess is defined by sidewalls in the FET region and is disposed above the recessed metal gate stack. A liner is formed overlying the sidewalls and the recessed metal gate stack and defines an inner cavity in the recess. A copper layer is formed overlying the liner and at least partially fills the inner cavity. The copper layer is etched to expose an upper portion of the liner while leaving a copper portion disposed in a bottom portion of the inner cavity. Copper is electrolessly deposited on the copper portion to fill a remaining portion of the inner cavity.

主权项

1. A method for fabricating an integrated circuit, the method comprising:
forming a metal gate stack in a FET trench formed in a FET region that comprises an interlayer dielectric material on a semiconductor substrate; etching the metal gate stack to form a recessed metal gate stack and a recess that is defined by sidewalls in the FET region and that is disposed along an upper section of the FET trench above the recessed metal gate stack; forming a liner overlying the sidewalls and the recessed metal gate stack and defining an inner cavity in the recess; forming a copper layer that overlies the liner and at least partially fills the inner cavity; etching the copper layer to expose an upper portion of the liner while leaving a copper portion disposed in a bottom portion of the inner cavity; and electrolessly depositing copper on the copper portion to fill a remaining portion of the inner cavity.