Method of manufacturing semiconductor device

摘要

A semiconductor device fabrication method particularly suitable for the fabrication of a 90 nm embedded flash memory is disclosed. The method includes: forming a dielectric layer having a first thickness over a first device region and forming a dielectric layer having a second thickness different from the first thickness over a second device region, the dielectric layer having a first thickness serving as a tunnel oxide layer of a split-gate structure, the dielectric layer having a second thickness serving as a gate oxide layer of a MOS transistor. The method enables the fabrication of a MOS transistor including a gate oxide layer with a desired thickness.

主权项

1. A method of manufacturing a semiconductor device, the semiconductor device comprising a split-gate structure and a metal oxide semiconductor (MOS) transistor, the method comprising the steps of:
1) providing a semiconductor substrate including a first device region and a second device region; 2) sequentially forming a first dielectric layer, a first conductive layer, a second dielectric layer, a second conductive layer, and a first etch stop layer over the semiconductor substrate; 3) forming a first window in the first etch stop layer in the first device region, removing a portion of the first etch stop layer that covers the second device region and forming a first isolation sidewall over each side face of the etched first etch stop layer; 4) forming a first trench in the first device region by performing an etching process using the first etch stop layer and the first isolation sidewalk as a mask until a surface of the semiconductor substrate is exposed; 5) depositing a third isolation dielectric layer and a third conductive layer over the resulting structure after the step 4); 6) removing a portion of each of the third isolation dielectric layer and the third conductive layer that covers the second device region; 7) sequentially depositing an additional conductive layer and an additional isolation dielectric layer over the resulting structure after the step 6); 8) sequentially depositing a second etch stop layer and a third etch stop layer over the resulting structure after the step 7); 9) removing a portion of each of the third etch stop layer, the second etch stop layer, the additional conductive layer and the additional isolation dielectric layer that covers the first device region, followed by a planarization process for exposing the first etch stop layer; 10) depositing a fourth etch stop layer over a surface of the third conductive layer filled in the first trench and removing the first and third etch stop layers using the fourth etch stop layer as a mask; 11) performing an etching process in the first device region using the fourth etch stop layer as a mask until a surface of the semiconductor substrate is exposed; and 12) removing undesirable portions of each of the additional conductive layer and the additional isolation dielectric layer in the second device region to form an electrode for connecting to an external power supply.