| 发明名称 |
PROCESSOR AND PROGRAM EXECUTION METHOD CAPABLE OF EFFICIENT PROGRAM EXECUTION |
| 摘要 |
A processor executes a plurality of tasks by switching a timeslot and iterating a plurality of timeslots. The processor includes a table in which tasks are defined in correspondence with timeslots. In the table, the number of timeslots to be held in one iteration is defined, for each of the timeslots a total time period during the predetermined number of iterations is designated, and a plurality of tasks are defined in correspondence with at least one of the timeslots. A timeslot is switched every time a predetermined period elapses. One task is selected and executed by referring to the table in correspondence with switching of timeslot. |
| 申请公布号 |
US2014196045(A1) |
申请公布日期 |
2014.07.10 |
| 申请号 |
US201414203569 |
申请日期 |
2014.03.11 |
| 申请人 |
Panasonic Corporation |
发明人 |
KURATA KAZUSHI;FURUKAWA KAZUYA;TANAKA TETSUYA;HIGAKI NOBUO;HAYASHI KUNIHIKO;KADOTA HIROSHI;KIYOHARA TOKUZO;KIMURA KOZO;NISHIDA HIDESHI;FUJII SHIGEKI;SUGIMURA TOSHIO |
| 分类号 |
G06F9/48 |
主分类号 |
G06F9/48 |
| 代理机构 |
|
代理人 |
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| 主权项 |
1. A processor for executing a plurality of tasks by switching a timeslot and iterating a plurality of timeslots, comprising:
a table in which tasks are defined in correspondence with timeslots, wherein in the table, (i) the number of timeslots to be held in one iteration is defined, (ii) for each of the timeslots a total time period during the predetermined number of iterations is designated and, (iii) a plurality of tasks are defined in correspondence with at least one of the timeslots, a timeslot is switched every time a predetermined period elapses, and one task is selected and executed by referring to the table in correspondence with switching of timeslot. |
| 地址 |
Osaka JP |
