SEMICONDUCTOR MEMORY DEVICE

摘要

A semiconductor memory device has a memory cell array having memory cells, each including first and second conduction type transistors, a peripheral circuit having the first and second conduction type transistors, a first conduction type memory cell array well region within the memory cell array region, a second conduction type memory cell array well region within the first conduction type memory cell array well region, a first conduction type peripheral circuit well region within the peripheral circuit region, a second conduction type peripheral circuit well region within the first conduction type peripheral circuit well region, and a second conduction type isolation region between the first conduction type memory cell array well region and the first conduction type peripheral circuit well region. At least a portion of first conduction type transistors of first conduction type transistors of the peripheral circuit is formed in the second conduction type isolation region.

主权项

1. A semiconductor memory device, comprising:
a memory cell array in which are disposed a plurality of memory cells, each including a first conduction type transistor and a second conduction type transistor; a peripheral circuit which includes the first conduction type transistor and the second conduction type transistor, and which controls access to memory cells in the memory cell array; a first conduction type memory cell array well region, which is within the region of the memory cell array, and in which are formed the second conduction type transistors of the plurality of memory cells; a second conduction type memory cell array well region, which is within the first conduction type memory cell array well region, and in which are formed the first conduction type transistors of the plurality of memory cells; a first conduction type peripheral circuit well region, which is within the region of the peripheral circuit, and in which is formed the second conduction type transistor of the peripheral circuit; a second conduction type peripheral circuit well region, which is within the first conduction type peripheral circuit well region, and in which is formed the first conduction type transistor of the peripheral circuit; and a second conduction type isolation region, which is disposed between the first conduction type memory cell array well region and the first conduction type peripheral circuit well region, wherein at least a portion of first conduction type transistors of first conduction type transistors of the peripheral circuit is formed in the second conduction type isolation region.