HIGH VOLTAGE SEMICONDUCTOR DEVICE

摘要

An n well region and an n−region surrounding the n well region are provided in the surface layer of a p−silicon substrate. The n−region includes breakdown voltage regions in which high voltage MOSFETs are disposed. The n well region includes a logic circuit region in which a logic circuit is disposed. A p− opening portion is provided between a drain region of each high voltage MOSFET and the logic circuit region. An n buffer region used as load resistances is provided between a second pick-up region and the drain region. The p−opening portion is provided between the n buffer region and logic circuit region. By so doing, it is possible to realize a reduction in the area of chips, and provide a high voltage semiconductor device having a level shift circuit with a high switching response speed.

主权项

1. A high voltage semiconductor device, comprising:
a second conductivity type semiconductor region provided on a first conductivity type semiconductor substrate; a logic circuit provided in the surface layer of the semiconductor region; an insulated gate field effect transistor having a second conductivity type source region provided on the outer peripheral side of the semiconductor region, a gate electrode provided on the semiconductor region via an insulating film, and a second conductivity type drain region provided in the surface layer of the semiconductor region so as to be spaced a predetermined distance from the outer peripheral edge of the semiconductor region; a second conductivity type pick-up region provided in the surface layer of the semiconductor region, away from the drain region, so as to be spaced the predetermined distance from the outer peripheral edge of the semiconductor region; a first conductivity type opening portion, reaching the semiconductor substrate from the surface of the semiconductor region, provided away from the drain region, second conductivity type pick-up region, and logic circuit, between the logic circuit and a region from the drain region to a portion of the semiconductor region extending to one drain region side portion of the second conductivity type pick-up region via a portion of the semiconductor region sandwiched between the drain region and second conductivity type pick-up region, and a load resistance formed of a portion of the semiconductor region sandwiched between the drain region and second conductivity type pick-up region.