SERIAL I/O USING JTAG TCK AND TMS SIGNALS

摘要

The present disclosure describes a novel method and apparatus of using the JTAG TAP's TMS and TCK terminals as a general purpose serial Input/Output (I/O) bus. According to the present disclosure, the TAP's TMS terminal is used as a clock signal and the TCK terminal is used as a bidirectional data signal to allow serial communication to occur between; (1) an IC and an external controller, (2) between a first and second IC, or (3) between a first and second core circuit within an IC.

主权项

1. An integrated circuit comprising:
A. functional circuitry; B test data leads including a test data in lead and a test data out lead; C. control leads including a test clock lead, and a test mode select lead; D. test circuitry coupled to the functional circuitry and coupled to the test data leads and the control leads, the test circuitry including:
i. first data path circuitry conveying test data to and from the functional circuitry over the test data leads;ii. second data path circuitry conveying test data to and from the functional circuitry over only the control leads; andiii. gating circuitry coupled to the first data path circuitry and the second data path circuitry and selecting the second data path circuitry to convey test data to and from the functional circuitry.