ADAPTIVE WORKLOAD BASED OPTIMIZATIONS COUPLED WITH A HETEROGENEOUS CURRENT-AWARE BASELINE DESIGN TO MITIGATE CURRENT DELIVERY LIMITATIONS IN INTEGRATED CIRCUITS

摘要

A dynamic system coupled with “pre-Silicon” design methodologies and “post-Silicon” current optimizing programming methodologies to improve and optimize current delivery into a chip, which is limited by the physical properties of the connections (e.g., Controlled Collapse Chip Connection or C4s). The mechanism consists of measuring or estimating power consumption at a certain granularity within a chip, converting the power information into C4 current information using a method, and triggering throttling mechanisms (including token based throttling) where applicable to limit the current delivery per C4 beyond pre-established limits or periods. Design aids are used to allocate C4s throughout the chip based on the current delivery requirements. The system coupled with design and programming methodologies improve and optimize current delivery is extendable to connections across layers in a multilayer 3D chip stack.

主权项

1. A method for integrated circuit (IC) chip and package design and IC chip operation comprising:
generating a data structure representing a current distribution relation between one or more current sources within a layout region of said chip, and one or more physical structures that deliver electrical current drawn by said current sources in said layout region as connected via grid networks in said IC; obtaining, using said data structure, an amount of current flow via said physical structures with respect to an amount of current drawn by current sources; and determining, using said current flow and current drawn amounts, locations of blocks having said one or more current sources, with respect to one or more objectives and constraints, said block locations effecting a non-uniform allocation of physical structures to blocks in one IC region than blocks in other regions having like one or more current sources, and, subsequently operating blocks in said regions at current draw activity levels according to the non-uniform allocation, wherein a programmed processor unit performs one or more said generating, obtaining, determining and operating.