REDUCING GATE HEIGHT VARIANCE DURING SEMICONDUCTOR DEVICE FORMATION

摘要

In general, aspects of the present invention relate to approaches for forming a semiconductor device such as a FET with reduced gate stack height variance. Specifically, when a gate stack height variance is detected/identified between a set of gate stacks, a hard mask layer and sets of spacers are removed from the uneven gate stacks leaving behind (among other things) a set of dummy gates. A liner layer and an inter-layer dielectric are formed over the set of dummy gates. The liner layer is then removed from a top surface (or at least a portion thereof) of the set of dummy gates, and the set of dummy gates are then removed. The result is a set of gate regions having less height variance/disparity.

主权项

1. A method for reducing gate height variance in a semiconductor device, comprising:
removing a hard mask layer and a set of spacers from a set of dummy gates; depositing a liner layer and an inter-layer dielectric (ILD) over the set of dummy gates; removing the liner layer from at least a portion of a top surface of the set of dummy gates; and removing the set of dummy gates.