CMOS CIRCUIT AND METHOD FOR FABRICATING THE SAME

摘要

The present technology provides a CMOS circuit capable of improving a polysilicon depletion ratio (PDR) of a PMOSFET and simultaneously preventing degradation in a gate insulating layer breakdown voltage of an NMOSFET and a method for manufacturing the same. The CMOS circuit according to the present technology comprises: a PMOSFET gate structure including a P-type doped silicon-containing electrode containing a P-type dopant, a first capturing material to capture the P-type dopant, and an activation accelerating material for accelerating activation of the P-type dopant; and an NMOSFET gate structure including a N-type doped silicon-containing electrode containing a N-type dopant, a second capturing material to capture the N-type dopant, and an activation suppressing material for suppressing activation of the N-type dopant. According to the resent technology, a carbon is used as the capturing material to increase concentration of the dopant in the interface between a gate insulating layer and the silicon-containing electrode, thereby improving the polysilicon depletion ratio of the NMOSFET and the PMOSFET. Furthermore, according to the present technology, it is possible to prevent a decrease in the breakdown voltage and threshold voltage of the gate insulating layer of the NMOSFET by deactivating surplus phosphorus by germanium. Furthermore, it is possible to accelerate activation of boron by the germanium.