| 摘要 |
Disclosed is a calibratable delay chain with a plurality of delay stages and adjustment circuitry to vary the delay of the stages in response to an input value. The calibration circuitry calibrates a delay of the chain, with calibration control circuitry which supplies the input value to the adjustment circuitry, output selection circuitry to select an output from a predetermined point along the delay chain, and a bypass path for bypassing the delay chain. Digital and analogue comparators compare the output from the delay chain and the output from the bypass path. The calibration control circuitry controls the output selection circuitry to output a signal from one point on the delay chain to the digital comparator and to change the input value to the adjustment circuitry in a first direction at a first rate until a change in an output value of the digital comparator value is detected. The calibration control circuitry responds to the detected change in output value of the digital comparator to control the output selection circuitry to output a signal from a further point on the delay chain to the analogue comparator and to change the input value in a second direction at a second rate starting from a value determined by the input value at which the digital comparators output value changed value, the second rate being slower than the first rate, a change in value output from the analogue comparator indicating an input value that provides a calibrated delay. |
