Sequential on-chip clock controller with dynamic bypass for multi-clock domain testing

摘要

A controller includes a clock control unit configured to provide a first output to test circuitry and a bypass unit configured to provide a second output to a further controller. The controller is configured to cause the bypass unit to output the second output and to optionally cause the clock control unit to output the first output.

主权项

1. A controller, comprising:
an input configured to receive an input sequential selection signal from a previous controller; a clock bit unit generating clock bit signals specifying clock pulses to generate; a clock control unit configured to receive the clock bit signals and responsively generate a pulsed output comprising the clock pulses specified by the clock bit signals; and a bypass unit configured to provide an output sequential selection signal for application to a further controller, wherein the bypass unit generates the output sequential selection signal in response to the received input sequential selection signal.