Memory hub architecture having programmable lane widths

摘要

A processor-based system includes a processor coupled to a system controller through a processor bus. The system controller is used to couple at least one input device, at least one output device, and at least one data storage device to the processor. Also coupled to the processor bus is a memory hub controller coupled to a memory hub of at least one memory module having a plurality of memory devices coupled to the memory hub. The memory hub is coupled to the memory hub controller through a downstream bus and an upstream bus. The downstream bus has a width of M bits, and the upstream bus has a width of N bits. Although the sum of M and N is fixed, the individual values of M and N can be adjusted during the operation of the processor-based system to adjust the bandwidths of the downstream bus and the upstream bus.

主权项

1. A memory apparatus comprising:
a first bus configured to have a first width; a second bus configured to have a second width concurrently with the first bus, wherein the first and second widths are variable, and wherein a sum of the first and second widths is constant; a plurality of buffers configurable as an input buffer or an output buffer, wherein the first width of the first bus and second width of the second bus are adjusted by configuring at least some of the plurality of buffers as either input buffers of output buffers; and a plurality of memory devices each configured to receive signals from a memory controller over the first bus and further configured to provide signals to the memory controller over the second bus.