Memory device page buffer configuration and methods

摘要

Memory devices and methods are described that include communication circuitry between page buffers in a memory array. Examples include communication circuitry that provide status information of page buffers that are directly adjacent to a given page buffer. The exchanged information can be used to adjust a given page buffer to compensate for effects in directly adjacent data lines that are being operated at the same time.

主权项

1. An apparatus, comprising:
a first data line associated with a first plurality of memory cells; a second data line directly adjacent to the first data line and coupled to a second plurality of memory cells; a first page buffer operable to control an activity of the first data line; a second page buffer operable to control an activity of the second data line; communication circuitry coupled between the first and second page buffers and operable to pass information about a voltage associated with the second data line to the first page buffer; and further including circuitry to raise a voltage on the first data line in response to the information about the voltage associated with the second data line.