发明名称 Optical proximity correction for active region design layout
摘要 The present disclosure provides an integrated circuit design method. In an example, a method includes receiving an integrated circuit design layout that includes an active region feature, a contact feature, and an isolation feature, wherein a portion of the active region feature is disposed between the contact feature and the isolation feature; determining whether a thickness of the portion of the active region feature disposed between the contact feature and the isolation feature is less than a threshold value; and modifying the integrated circuit design layout if the thickness is less than the threshold value, wherein the modifying includes adding a supplementary active region feature adjacent to the portion of the active region feature disposed between the contact feature and the isolation feature.
申请公布号 US8775982(B2) 申请公布日期 2014.07.08
申请号 US201313926284 申请日期 2013.06.25
申请人 Taiwan Semiconductor Manufacturing Company, Ltd. 发明人 Lin Mei-Hsuan;Lu Chih-Chan;Lin Chih-Hsun;Chao Chih-Kang;Wang Ling-Sung;Wang Jen-Pan
分类号 G06F17/50;H01L25/00;H01L29/788;H01L27/12;H03K19/00 主分类号 G06F17/50
代理机构 Haynes and Boone, LLP 代理人 Haynes and Boone, LLP
主权项 1. A method comprising: receiving an integrated circuit design layout that includes an active region feature, a contact feature, and an isolation feature, wherein a portion of the active region feature is disposed between the contact feature and the isolation feature; determining whether a thickness of the portion of the active region feature disposed between the contact feature and the isolation feature is less than a threshold value; modifying the integrated circuit design layout if the thickness is less than the threshold value, wherein the modifying includes adding a supplementary active region feature adjacent to the portion of the active region feature disposed between the contact feature and the isolation feature during an optical proximity correction (OPC) process; and fabricating a mask according to the integrated circuit design layout.
地址 Hsin-Chu TW