发明名称 Power-rail electro-static discharge (ESD) clamp circuit
摘要 A power-rail ESD clamp circuit with a silicon controlled rectifier and a control module is provided. The silicon controlled rectifier is connected to a high voltage level and a low voltage level for bearing a current flow. The control module is connected to the silicon controlled rectifier in parallel, and includes a PMOS, a NMOS, at least one output diode, a resistor and a conducting string. The silicon controlled rectifier is a P+ or N+ triggered silicon controlled rectifier. By employing the novel power-rail ESD clamp circuit, it is extraordinarily advantageous of reducing both a standby leakage current and layout area while implementation.
申请公布号 US8773826(B2) 申请公布日期 2014.07.08
申请号 US201213598194 申请日期 2012.08.29
申请人 Amazing Microelectronic Corp. 发明人 Altolaguirre Federico Agustin;Ker Ming-Dou;Jiang Ryan Hsin-Chin
分类号 H02H9/00 主分类号 H02H9/00
代理机构 Muncy, Geissler, Olds & Lowe, P.C. 代理人 Muncy, Geissler, Olds & Lowe, P.C.
主权项 1. A power-rail Electro-Static Discharge (ESD) clamp circuit comprising: a silicon controlled rectifier, connected to a high voltage level VDD and a low voltage level VSS for bearing a current flow; and a control module, connected to said silicon controlled rectifier in parallel, said control module connecting between said high voltage level VDD, said low voltage level VSS and a trigger node of said silicon controlled rectifier, wherein said silicon controlled rectifier is a P+ triggered silicon controlled rectifier, and said control module comprises: a PMOS, connected to said high voltage level VDD; an NMOS, connected to said low voltage level VSS; at least one output diode, connected between said PMOS and said NMOS, wherein said trigger node of said P+ triggered silicon controlled rectifier is connecting to said at least one output diode, and said PMOS, said NMOS and said at least one output diode are connecting serially together; a resistor, parallel connected to said P+ triggered silicon controlled rectifier, said PMOS and said NMOS, one end of said resistor connecting to said high voltage level VDD; and a conducting string, comprising at least one conducting element connected to said NMOS, wherein said conducting string is connecting between the other end of said resistor, said PMOS, and said low voltage level VSS.
地址 New Taipei TW