| 摘要 |
The present invention relates to a duty cycle correction circuit capable of correcting a duty rate of a clock signal. Provided is a duty cycle correction circuit comprising a control signal generating unit generating a duty control signal for controlling the duty rate of the clock signal by reflecting a first or second operation type, an operation type setting unit setting the first or second operation type in response to an operation type selection signal corresponding to the duty rate of the clock signal, and a clock correcting unit correcting the clock signal in response to the duty control signal. |
