主权项 |
1. An apparatus comprising:
a phase detector configured to generate an error signal representing a phase difference between
(i) a recovered clock signal, and(ii) a serial data stream, wherein the serial data stream includes a first clock signal, and wherein a frequency and a phase of the first clock signal vary; and a phase selector configured to provide the recovered clock signal based on (i) a first sample of the error signal for a first cycle of the first clock signal, and (ii) a second sample of the error signal for a second cycle of the first clock signal, wherein
the phase selector is configured to provide the recovered clock signal based on (i) a first sum of a first plurality of samples of the error signal for first consecutive cycles of the first clock signal, and (ii) a second sum of a second plurality of samples of the error signal for second consecutive cycles of the first clock signal, andthe first plurality of samples include the first sample and the second sample. |