| 发明名称 | Fabricating method of transistor | ||
| 摘要 | A fabricating method of a transistor is provided. A patterned sacrificed layer is formed on a substrate, wherein the patterned sacrificed layer includes a plurality of openings exposing the substrate. By using the patterned sacrificed layer as a mask, a doping process is performed on the substrate, thereby forming a doped source region and a doped drain region in the substrate exposed by the openings. A selective growth process is performed to form a source and a drain on the doped source region and the doped drain region, respectively. The patterned sacrificed layer is removed to expose the substrate between the source and the drain. A gate is formed on the substrate between the source and the drain. | ||
| 申请公布号 | US8772119(B2) | 申请公布日期 | 2014.07.08 |
| 申请号 | US201113236656 | 申请日期 | 2011.09.20 |
| 申请人 | Nanya Technology Corporation | 发明人 | Su Kuo-Hui;Chen Yi-Nan;Liu Hsien-Wen |
| 分类号 | H01L21/336 | 主分类号 | H01L21/336 |
| 代理机构 | Jianq Chyun IP Office | 代理人 | Jianq Chyun IP Office |
| 主权项 | 1. A fabricating method of a transistor, comprising: forming a patterned sacrificed layer on a substrate, wherein the patterned sacrificed layer includes a plurality of openings exposing the substrate; by using the patterned sacrificed layer as a mask, performing a doping process on the substrate, thereby forming a doped source region and a doped drain region in the substrate exposed by the openings; performing a selective growth process to form a source and a drain on the doped source region and the doped drain region, respectively; removing the patterned sacrificed layer to expose the substrate between the source and the drain; and forming a gate on the substrate between the source and the drain, wherein a height of the gate is substantially the same as a height of the source and the drain. | ||
| 地址 | Taoyuan TW | ||