Performing a cyclic redundancy checksum operation responsive to a user-level instruction

摘要

In one embodiment, the present invention includes a method for receiving incoming data in a processor and performing a checksum operation on the incoming data in the processor pursuant to a user-level instruction for the checksum operation. For example, a cyclic redundancy checksum may be computed in the processor itself responsive to the user-level instruction. Other embodiments are described and claimed.

主权项

1. A processor comprising:
a plurality of cores, wherein at least one of the cores comprises:
a cache;a plurality of general purpose registers; anda plurality of execution units comprising a store data unit, an integer execution unit, a floating point execution unit, and a single instruction multiple data (SIMD) execution unit, wherein at least one of the plurality of execution units comprises logic to:
perform a cyclic redundancy check (CRC) operation in response to one or more CRC32 instructions executed in a 32-bit mode of operation or a 64-bit mode of operation, wherein the logic is to perform the CRC operation on one of a plurality of data sizes, including a data size of 8-bits, 16-bits, and 32-bits, and wherein the one or more CRC32 instructions are to indicate the data size on which to perform the CRC operation.