Methods to reduce output voltage ripple in constant on-time DC-DC converters

摘要

According to one aspect of the teachings herein, a DC-to-DC converter operates according to an advantageous constant on-time topology that reduces output voltage ripple during light load conditions. The converter produces an output voltage by driving high-side and low-side switches in an inductor-based switching circuit, and regulates the output voltage by varying the on-time of a low-side switch, while holding the on-time of the high-side switch constant. Advantageously, the converter shortens the on-time of the high-side switch during light load conditions, which reduces the output voltage ripple. Thus, the converter may be understood as using a first, constant on-time for the high-side switch during “normal” operations and a second, shorter on-time for the high-side switch during light load conditions.

主权项

1. A constant on-time DC-to-DC converter comprising:
a regulation control circuit configured to regulate an output voltage generated at an output of a switching circuit supplied by an input voltage, based on generating high-side and low-side pulses for driving high-side and low-side switches, respectively, in the switching circuit according to a switching cycle that has a variable on-time for the low-side switch and, for a normal mode of operation, a constant on-time for the high-side switch; a feedback circuit configured to provide a regulation feedback signal to the regulation control circuit, for controlling the variable on-time of the low-side switch as needed to maintain regulation of the output voltage; and an on-time control circuit included in said regulation control circuit that is configured to decrease output voltage ripple in the output voltage during a power saving mode of operation by shortening the on-time of the high-side switch, as compared to the constant on-time used for the high-side switch during the normal mode of operation, the on-time control circuit comprising
a one-shot timer configured to set the on-time of the high-side switch in dependence on a charging current that increases when the regulation control circuit operates in the power saving mode, wherein higher values of the charging current result in shorter on-times for the high-side switch, anda current source circuit configured to generate the charging current in dependence on the input voltage, such that, for a given input voltage and given programmed value, it has a first magnitude during the normal mode of operation; wherein the feedback circuit includes an additional current circuit that provides a decaying current after each low-side pulse, such that more decay occurs during extended switching cycles used in power saving mode, and wherein said charging current varies inversely to said decaying current; and wherein said regulation control circuit is configured to enter said power saving mode of operation responsive to detecting light load conditions and to reduce switching losses in said switching circuit while operating in the power saving mode by inserting a variable dead time into the switching cycle.