Combination FinFET and planar FET semiconductor device and methods of making such a device

摘要

A device includes a plurality of trenches and fins defined in a substantially un-doped layer of semiconducting material, a gate insulation layer positioned on the fins and on the bottom of the trenches, a gate electrode and a device isolation structure. One method disclosed herein involves identifying a top width of each of a plurality of fins and a depth of a plurality of trenches to be formed in a substantially un-doped layer of semiconducting material, wherein, during operation, the device is adapted to operate in at least three distinguishable conditions depending upon a voltage applied to the device, performing at least one process operation to define the trenches and fins in the layer of semiconducting material, forming a gate insulation layer on the fins and on a bottom of the trenches and forming a gate electrode above the gate insulation layer.

主权项

1. A method of forming a device comprised of a plurality of fins and a plurality of trenches formed in a substantially un-doped layer of semiconducting material, the method comprising:
identifying a top width of each of said plurality of fins and a depth of each of said plurality of trenches such that, during operation, said device is adapted to operate in at least three distinguishable conditions depending upon a voltage applied to said device; performing at least one process operation to define said plurality of trenches in said substantially un-doped layer of semiconducting material, wherein said trenches define said plurality of fins in said substantially un-doped layer of semiconducting material; forming a gate insulation layer on said plurality of fins and on a bottom surface of each of said trenches; and forming a gate electrode above said gate insulation layer.